silego technology, inc. SLG7NT41021 ddr sequencer and fet driver SLG7NT41021_ds_r10 5 SLG7NT41021_gp_r006 rev 1.0 5 revised april 20 , 2016 general description features ? low power consumption ? pb - free / rohs compliant ? halogen - free ? s t qfn - 20 package output summary ? 4 outputs ? push pull 1x ? 5 outputs ? open drain nmos 1x ? 1 output ? 3 - state 1x pin configuration 1 2 3 4 5 6 7 11 8 9 10 20 19 18 s t q fn - 20 top view 12 13 14 15 16 17 vdd SLG7NT41021 gnd vddq_pwrgd slp_s3_n nfet_v5dual_usb_n ddr_nmos_q3 v5s_mon pfet_v5dual_usb ps1_out slp_s4_n +v5_v12_ddr sus_warn_n ps1 sus_ack_n v12s_mon pfet_5v dual_ddr nfet_5vdual_ddr_ n v5s_pwrgd ddr_pmos_q2 ddr_pmos_q1 silego SLG7NT41021 is a low power and small form device. the soc is housed in a 2mm x 3mm stqfn package which is optimal for using with small devices.
page 2 2 ddr sequencer and fet driver SLG7NT41021_ds_r10 5 SLG7NT41021 p in configuration pin # pin name type pin description 1 vdd pwr supply voltage 2 vddq_pwrgd digital input digital input without schmitt trigger 3 slp_s3_n digital input digital input without schmitt trigger 4 nfet_v5dual_usb_n digital output open drain nmos 1x 5 ddr_nmos_q3 digital output push pull 1x 6 v5s_mon analog input/output analog input/output 7 pfet_v5dual_usb digital output open drain nmos 1x 8 ps1_out digital output open drain nmos 1x 9 slp_s4_n digital input digital input without schmitt trigger 10 +v5_v12_ddr analog input/output analog input/output 11 gnd gnd ground 12 sus_warn_n digital input digital input without schmitt trigger 13 ps1 digital input digital input without schmitt trigger 14 sus_ack_n digital output open drain nmos 1x 15 v12s_mon analog input/output analog input/output 16 ddr_pmos_q2 digital output push pull 1x 17 ddr_pmos_q1 digital output push pull 1x 18 pfet_5vdual_ddr digital output 3 - state output 1x 19 nfet_5vdual_ddr_n digital output push pull 1x 20 v5s_pwrgd digital output open drain nmos 1x ordering information part number package type SLG7NT41021v v= s tqfn - 20 SLG7NT41021vtr vtr= s tqfn - 20 ? tape and reel (3k units)
page 3 3 ddr sequencer and fet driver SLG7NT41021_ds_r10 5 SLG7NT41021 absolute maximum conditions parameter min. max. unit v high to gnd - 0.3 7 v voltage at input pins - 0.3 7 v current at input pin - 1.0 1.0 ma storage temperature range - 65 125 c junction temperature -- 150 c esd protection (human body model) 2000 -- v esd protection (charged device model) 13 00 -- v moisture sensitivity level 1 electrical characteristics (@ 25c, unless otherwise stated) symbol parameter condition/note min. typ. max. unit v dd supply voltage 1.71 3.3 5.5 v t a operating temperature - 40 25 85 c i q quiescent current static inputs and outputs -- 90 -- a v o maximal voltage applied to any pin in high - impedance state -- -- vdd v i o maximal average or dc current (note 1) per each chip side (pin2 - pin10, pin12 - pin20) -- -- 90 ma v ih high - level input voltage logic input, at vdd=1.8v 1.10 -- vdd v logic input, at vdd=3.3v 1.78 -- vdd logic input, at vdd=5.0v 2.64 -- vdd v il low - level input voltage logic input, at vdd=1.8v -- -- 0.69 v logic input, at vdd=3.3v -- -- 1.21 logic input, at vdd=5.0v -- -- 1.84 i ih high - level input current logic input pins; v in = vdd - 1.0 -- 1.0 a i il low - level input current logic input pins; v in = 0v - 1.0 -- 1.0 a v oh high - level output voltage push pull & pmos od, i oh = 100ua, 1x driver, at vdd=1.8 v 1.69 1.789 -- v push pull & pmos od, i oh = 3ma, 1x driver, at vdd=3.3 v 2.735 3.12 -- push pull & pmos od, i oh = 5ma, 1x driver, at vdd=5.0 v 4.19 4.78 -- v ol low - level output voltage push pull, i ol = 100ua, 1x driver, at vdd=1.8 v -- 0.008 0.03 v open drain, i ol = 100ua, 1x driver, at vdd=1.8 v -- 0.005 0.020 push pull, i ol = 3ma, 1x driver, at vdd=3.3 v -- 0.13 0.228 open drain, i ol = 3ma, 1x driver, at vdd=3.3 v -- 0.080 0.147
page 4 4 ddr sequencer and fet driver SLG7NT41021_ds_r10 5 SLG7NT41021 push pull, i ol = 5ma, 1x driver, at vdd=5.0 v -- 0.157 0.270 open drain, i ol = 5ma, 1x driver, at vdd=5.0 v -- 0.102 0.180 i oh high - level output current push pull & pmos od, v oh = v dd - 0.2, 1x driver, at vdd=1.8 v 1.066 1.703 -- ma push pull & pmos od, v oh = 2.4 v, 1x driver, at vdd=3.3 v 6.045 12.08 -- push pull & pmos od, v oh = 2.4 v, 1x driver, at vdd=5.0 v 22.08 34.04 -- i ol low - level output current push pull, v ol =0.15v, 1x driver, at vdd=1.8 v 0.917 1.689 -- ma open drain, v ol =0.15v, 1x driver, at vdd=1.8 v 1.375 2.534 -- push pull, v ol =0.4v, 1x driver, at vdd=3.3 v 4.875 8.244 -- open drain, v ol =0.4v, 1x driver, at vdd=3.3 v 7.313 12.37 -- push pull, v ol =0.4v, 1x driver, at vdd=5.0 v 7.215 11.58 -- open drain, v ol =0.4v, 1x driver, at vdd=5.0 v 10.82 17.38 -- v acmp0 analog comparator threshold voltage acmp0 threshold including input offset, reference voltage variation and hysteresis, at temperature 25c. 934 -- 965 mv acmp0 threshold including input offset, reference voltage variation and hysteresis, at temperature - 40c +85c (note 1) 886 -- 994 v acmp1 analog comparator threshold voltage acmp1 threshold including input offset, reference voltage variation and hysteresis, at temperature 25c. 984 -- 1016 mv acmp1 threshold including input offset, reference voltage variation and hysteresis, at temperature - 40c +85c (note 1) 933 -- 1046 v acmp3 analog comparator threshold voltage acmp3 threshold including input offset, reference voltage variation and hysteresis, at temperature 25c. 934 -- 965 mv acmp3 threshold including input offset, reference voltage variation and hysteresis, at temperature - 40c +85c (note 1) 886 -- 994 t dly0 delay0 time at temperature 25c 4.47 4.98 5.23 ms at temperature - 40c +85c (note 1) 4.05 4.98 6.19 t dly1 delay1 time at temperature 25c 108.37 140 167.13 s at temperature - 40c +85c (note 1) 98.18 140 197.87 t su start up time from vdd rising past 1.35 v -- 0.3 -- ms 1. guaranteed by design.
page 5 5 ddr sequencer and fet driver SLG7NT41021_ds_r10 5 SLG7NT41021 package top marking datasheet revision programming code number locked status part code revision date 1.05 006 l 41021 ac 04/20/2016 the ic security bit is locked/set for code security for production unless otherwise specified. revision number is not changed for bit locking .
page 6 6 ddr sequencer and fet driver SLG7NT41021_ds_r10 5 SLG7NT41021 package drawing and dimensions 20 lead s t q fn package jedec mo - 220, variation wece ic net weight: 0.015 g
page 7 7 ddr sequencer and fet driver SLG7NT41021_ds_r10 5 SLG7NT41021 tape and reel specification package type # of pins nominal package size (mm) max units reel & hub size (mm) trailer a leader b pocket (mm) per reel per box pockets length (mm) pockets length (mm) width pitch s t q fn 20l 2 x3 mm 0.4p green 20 2x3x0.55 3000 3000 178/60 100 400 100 400 8 4 carrier tape drawing and dimensions package type pocket btm length (mm) pocket btm width (mm) pocket depth (mm) index hole pitch (mm) pocket pitch (mm) index hole diameter (mm) index hole to tape edge (mm) index hole to pocket center (mm) tape width (mm) a0 b0 k0 p0 p1 d0 e f w s t q fn 20l 2 x3 mm 0.4p green 2.2 3.15 0.76 4 4 1.5 1.75 3.5 8 refer to eia - 481 specifications recommended reflow soldering profile please see ipc/jedec j - std - 020: latest revision for reflow profile based on package volume of 3.3 mm 3 (nominal). more information can be found at www.jedec.org .
page 8 8 ddr sequencer and fet driver SLG7NT41021_ds_r10 5 SLG7NT41021 silego website & support silego technology website silego technology provides online support via our website at http://www.silego.com/ .this website is used as a means to make files and information easily available to customers. for more information regarding silego green products, please visit: http://greenpak.silego.com/ http://greenpak2.silego.com/ http://greenpak3.silego.com/ http://greenfet.silego.com/ http://greenfet2.silego.com/ http://greenclk.silego.com/ products are also available for purchase directly from silego at the silego online store at http://www.silego.com/ silego technical support datasheets and errata, application notes and example designs, user guides, and hardware support docu ments and the latest software releases are available at the silego website or can be requested directly at info@silego.com. for specific greenpak design or applications questions and support please send e - mail requests to greenpak@silego.com users of silego products can receive assistance through several channels: online training silego technology has live training assistance and sales support available at http://www.silego.com/ . please contact us to schedule a 1 on 1 training session with one of our application engineers. contact your local sales representative customers can contact their local sales representative or f ield application engineer (fae) for support. local sales offices are also available to help customers. more information regarding your local representative is available at th e silego website or send a request to info@silego.com contact silego directly silego can be contacted directly via e - mail at info@silego.com or user submission form, located at the following url: http://support.silego.com/ other information the latest silego technology press releases, listing of seminar s and events, listings of world wide silego technology offices and representatives are all available at http://www.silego.com/ this product has been designed and qualified for the consumer market. applications or uses as critical components in life support devices or systems are not authorized. silego technology does not assume any liability arising out of such applications or uses of its products. silego technology reserves the right to improve product design, functions and reliability without notice
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